4 Marks Questions

Question 14 Marks

Describe with diagram the working method of $p-n-p$ and $n-p-n$ transistors.

Answer

$n-p-n$ transistor working: In this transistor, the forward bias causes the electrons in the $n$-type emitter to flow towards the base which constitutes the emitter current $I_E$. When these electrons flow towards the base , it got combined with the majority carriers i.e., holes of the base. As we know, the base is very thin and lightly doped, therefore, to constitute base current I_B only a few electrons i.e., less than 5% got combine with the holes.

The remaining electrons i.e., more than 95% passes through the collector region to constitute collector current I. In this way, the entire emitter current flows in the collector circuit. Therefore, it is clear that the emitter current is equal to the sum of collector current and base current.
i.e., $I_E=I_B+I_C$
$p-n-p$ transistor working: In this transistor, the forward bias causes the holes in the $p$-type emitter to flow towards the base which constitutes the emitter current $I_{E}$.

When these holes flow towards the base, it got combined with the majority carriers i.e., electrons of the base. As we know, the base is very thin and lightly doped, therefore to constitute base current, only a few holes i.e., less than 5% got combine with the electrons. The remaining holes i.e., more than 95% passes through the collector region to constitute collector current $I_{C}$. In this way, the entire emitter current flows in the collector circuit.

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Question 24 Marks

Mention the difference between $n$-type and $p$-type semiconductors.

Answer

Difference betwen $n$-type and $p$-type semiconductors

$n$-type Semiconductor	$p$-type Semiconductor
1. It is an extrinsic semicon-ductor obtained by adding a pentavalent impurity to a pure intrinsic semi-conductor.	It is also an extrinsic semi-conductor obtained by adding a trivalent impurity to a pure intrinsic semiconductor.
2. The impurity atoms added provide extra free electrons to the crystal lattice and are called donor atoms.	The impurity atoms added create holes in the crystal lattice and are called acceptor atoms because the created holes accept electrons.
3. The electrons are majority carriers and the holes are minority carriers.	The holes are majority carriers and the electrons are mino-rity carriers.
4. The electron concentration is much more than the hole concentration $\left(n_e \gg n_h\right)$.	The hole concentration is much more than the electron concentration $\left(n_h \gg n_e\right)$.

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Question 34 Marks

What is logic gate? Differentiate between AND gate and OR gate.

Answer

Logic Gate : "A logic gate is defined as a digital circuit which follows some logical relationship between the input and output voltages."
The digital circuit of a gate either allows a signal to pass through it or stop it, so it is called a gate.
The logic gates are building blocks of digital electronics. They are used in digital electronics to change one voltage level i.e., input voltage into another level i.e., output voltage following some logical conditions relating them. Logic gates can be made by using simple switches, semiconductor diodes and transistors.
A logic gate may have one or more inputs but it has only one output. There are three basic logic gates as given below:
(i) OR gate, (ii) AND gate and (iii) NOT gate.
Each basic gate is represented by a symbol and its function is described by a Boolean expression or by a table known as truth table, which represents the relation between the possible values of input and output voltage in tabular form.

Difference between AND Gate and OR Gate

AND Gate	OR Gate
In this gate when both the inputs are 1 then output is also 'equal to 1'. Otherwise output is always zero.	In this gate when both the inputs are zero, then output is also zero otherwise output is always 1.

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Question 44 Marks

Using only NAND gate make combination diagrams to obtained NOT, AND and OR gates.

Answer

(1) To obtain Basic Gates from NAND Gates :
To obtain NOT gate from NAND gate: When the two inputs of a NAND gate are connected with each other they become a single input. In this condition, NAND gate behaves as a NOT gate Fig. 1.