Output \(Z\) of single three input gate is that of \(AND\) gate.
\(A\) | \(B\) | \(C\) | \(X \overline {AB}\) | \(Y= \overline {BC}\) | \(Z= \overline {X+Y}\) |
\(0\) | \(0\) | \(0\) | \(1\) | \(1\) | \(0\) |
\(1\) | \(0\) | \(0\) | \(1\) | \(1\) | \(0\) |
\(0\) | \(0\) | \(1\) | \(1\) | \(1\) | \(0\) |
\(1\) | \(0\) | \(1\) | \(1\) | \(1\) | \(0\) |
\(0\) | \(1\) | \(0\) | \(1\) | \(1\) | \(0\) |
\(1\) | \(1\) | \(0\) | \(0\) | \(1\) | \(0\) |
\(0\) | \(1\) | \(1\) | \(1\) | \(0\) | \(0\) |
\(1\) | \(1\) | \(1\) | \(0\) | \(0\) | \(1\) |