Physics M.C.Q (1 Marks)

Depletion region is a region near the $p-n$ junction where flow of charge carriers $($free electrons and holes$)$ is reduced over a given period and finally results in zero charge carriers.The width of depletion region which is generally $1\mu m$, depends on the amount of impurities added to the semiconductor. Impurities are the atoms $($pentavalent and trivalent atoms$)$ added to the semiconductor to improve its conductivity.
hence answer is $1\mu$ m and correct option is $D -$ none of these.

In circuit $(a)$, the diode is forward biassed. So, it offers negligible resistance to the flow of current and can thus be replaced by a short circuit. Now, the capacitor charge will leak through the resistance and decay exponentially with time.
Capacitor charge $=\frac{\text{VC}}{\text{e}}$
In circuit $(b),$ the diode is reverse biassed. So, it offers infinite resistance to the current flow and can thus be replaced by an open circuit. As the circuit is open now, no current can flow across the resistance. So, the charge in the capacitor cannot leak through the resistor.
Capacitor charge $= VC$

$\text{OR}$ gate has the property that output is one when any one of the inputs is one and zero only when all inputs are zero. From the truth table, it can be seen that the above two properties are satisfied.

In Si and Ge at room temperature $(300K);$ the energy band gap is low as the result of which electrons in the covalent bonds gain kinetic energy, they break the bond and move to conduction band.
A hole is also created in the valence band. So the number of free electrons for conduction is significant in $Si$ and Ge.
The energy band gap in case of carbon is high as the result of which there are not significant number of electrons in the conduction band even at room temperature.

When a semiconductor is doped with a donor type such as arsenic or phosphorous, which has five valence electrons, the donor atom replaces the $Si$ or $Ge$ atom. As a result, four out of the five electrons of the donor atom form a covalent bond by sharing an electron with four atoms of silicon. However, the fifth electron is free to move. Also, due to the breaking up of covalent bonds at room temperature, equal number of electrons and holes are produced. Thus, the total number of holes in the $n-$type semiconductor is less compared to the number of free electrons.

It is a $p-n-p,$ transistor. The Lead marked with the arrow is the emitter. It tells the direction of the flow of the holes i.e, the flow of conventional current.

The output is $0$ only when the two inputs are $1.$
The output is $1$ when any of the input is zero.
This is the characteristic of a $\text{NAND}$ gate.

In an intrinsic semiconductor, the number density of electrons is equal to the number density of holes i.e ne $=$ nh.
Since there is no doping, no extra hole or electron is produced.

$\text{NOT}$ gate yields the reverse of the input signal in output, thus when an input signal $1$ is applied to a $\text{NOT}$ gate, its output is $0.$

Only one logic gate has one input terminal i.e. $\text{NOT}$ gate.

When a diode is connected in a Zero Bias condition, no external potential energy is applied to the $PN$ junction. However if the diodes terminals are shorted together, a few holes $($majority carriers$)$ in the $P-$type material with enough energy to overcome the potential barrier will move across the junction against this barrier potential. This is known as the Forward Current.
Likewise, holes generated in the $N-$type material $($minority carriers$)$, find this situation favourable and move across the junction in the opposite direction. This is known as the Reverse Current and is referenced as $IR$. This transfer of electrons and holes back and forth across the $PN$ junction is known as diffusion.
Then an Equilibrium or balance will be established when the majority carriers are equal and both moving in opposite directions so that the net result is zero current flowing in the circuit. When this occurs the junction is said to be in a state of Dynamic Equilibrium.

In Boolean algebra, $A + B = Y$ implies that $Y$ exists when $A$ exists or $B$ exists or both $A$ and $B$ exist.

When the reverse voltage across a diode is very large, the valance electrons become free due to applied high electric field and get enough acceleration to make other electrons free, thus create a lot of electron-hole pairs in a short time. As the number of charge carriers increases, current also increases.
Therefore, at breakdown voltage, the rate of creation of hole$-$electron pairs is increased leading to the increase in current.

The image given shows a diode $\text{OR}$ circuit. $R$ is connected from the output to ground to provide bias current for the diodes. Any positive voltage will represent a logic $1$ state and the summing of currents through multiple diodes does not change the logic level.

Generally $Si$ is a semiconductor. In $p$ type semiconductor acceptor level lies near the valence band and each donor atom contribute one electron. $p-n$ junction electrically neutral because total charge is zero.

Semiconductors in their natural state are poor conductors because a current requires the flow of electrons, and semiconductors have their valence band filled, preventing the entry flow of new electrons.
Thus semi$-$conductors allows a large current to pass through them.

The avalanche breakdown in $p-n$ junction is due to cumulative effect of conduction band electron. In reverse bias, due to applied electric field, electrons acquire enough energy to free more electron bound to the atom. The abundant number of electron$-$hole pairs are created for conduction, this is cumulative effect.

$\text{NAND}$ and $\text{NOR}$ gates are known as universal gates. Any one of these gates can be used to implement any kind of logic gate. This kind of feasibility is does not exist with other gates i.e. any other gate cannot solely implement all logic gates. For example, $\text{AND}$ gate cannot be implemented using an $\text{OR}$ gate and vice$-$versa. The implementation of $\text{NAND}$ and $\text{NOR}$ gates to generate other logic gates is shown above.

When a $p‒n$ junction is formed then because of the difference in the concentration of charge carriers in the two regions, electrons from the $n$ region move to the $p$ region and holes from the $p$ region move to the $n$ region. Since the direction of the current is always opposite to the motion of electron, the direction of the current is from the $p$ side to the n side.
Similarly, when the junction is forward biassed, the positive terminal of the battery is connected to the pside of the $p‒n$ junction and the negative terminal of the battery is connected to the n side of the $p‒n$junction. As a result, electrons in the n side of the $p‒n$ junction are repelled by the negative terminal of the battery and they move to the $p$ side, where the positive terminal of the battery attracts them. Similarly, holes from the $p$ side of the $p‒n$ junction are repelled by the positive terminal of the battery and they move to the $n$ side, where the negative terminal of the battery attracts them. Thus, they give diffusion current from the $p$ side to the $n$ side across the $p‒n$ junction.
In reverse biassing, there is no flow of majority carriers across the junction; hence, there is not diffusion current. Here, the flow of majority carriers is opposed by the applied voltage.

Majority carrier in a $n −$ type semiconductor are holes. This statement is false.
Since, in $n−$type semiconductor, the pentavalent impurity atoms donate electrons o the host crystal and the semiconductor doped with donars $($pentavalent impurity$)$ is called $n −$ type semiconductor.
Therefore majority carrier in a $n−$type semiconductor are electrons.

A $\text{NOT}$ gate inverts the input signal which is the same as complementing a signal or changing the logic in a digital circuit. This means that when the input to the $\text{NOT}$ gate is logic $'0'$, the output is logic $'1'$. However, it does not stop a signal.

In intrinsic semiconductors, $n = p$. Hence, at room temperature, no free electrons are available for conduction.
If some energy is supplied to the atoms of intrinsic semiconductor, the covalent bonds will break and electrons will be freed, each electron will leave behind a hole and capture a new hole the process will continued and charge flows through intrinsic semiconductor.
Thus, in intrinsic semiconductor conductivity is due to breaking of covalent bonds.

At room temperature, in impure semiconductors some free charge carriers are available for conduction due to impurity atoms. But in pure, i.e., intrinsic semiconductors, $n = p.$
Hence, at room temperature no free electrons are available for conduction. If the temperature is increased the covalent bonds will break and electrons will be freed, each electron will leave behind a hole and capture a new hole the process will continued and charge flows through intrinsic semiconductor.
Thus, its conductivity is only due to breaking of covalent bonds.

The truth table of $\text{NAND}$ gate is shown as above, which implies that if at least one of the input is low then the output is high.